HT85F2270 datasheet(152/226 Pages) HOLTEK

152 / 226 page

Rev. 1.00

1�� of ��6

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Standard 8051 8-Bit Flash MCU

HT85F2260/HT85F2270/HT85F2280

Programmable Clock Output Mode

The Programmable Clock Output mode is related to Module 0. With this function, Timer 2 can

generate various clock outputs. This function is enabled by the T2OE bit in the T2CON1 register.

The output initial state is decided by the T2OI bit in the T2CON1 register. The Timer 2 enable

control or clock source is selected by the T2I1 and T2I0 bits in the T2CON register. The clock

source is further decided by the T2PRE1 and T2PRE0 bits in the TMPRE register. The data in

the TL2 and TH2 registers decides the clock duty cycle. If the counter overflows, then the CRCL

and CRCH registers will be auto-reloaded to the TL2 and TH2 registers. There are two ways

to implement a 50% duty cycle clock output on the T2 pin. One method is to input the external

clock for Timer/Counter 2 and the other is to output a 50% duty cycle clock ranging from 61HZ to

4MHz when the system clock is selected as 16MHz. To configure the Timer/Counter 2 as a clock

generator, the T2I1 and T2I0 bits in the T2CON register must be set as 0 and 1 respectively to start

the timer and the T2OE bit in the T2CON1 register must be set as well.

The clock-out frequency depends on the system frequency and the reload value of Timer 2 capture

registers (CRCH, CRCL) as shown in this equation:

Clock Out Frequency

Timer 2 Clock Frequency

2 * (65536 - [CRCH, CRCL])

The Timer 2 Clock frequency is dependent on the T2PRE0 and T2PRE1 bits. The accompanying

diagram illustrates the Timer2 Clock output basic operation block diagram.

Prescaler

P1.6/T�

T�OE

fSYS

T�PRE[1:0]

/�

TF�

Interrupt

TH�/TL�

CRCH/CRCL

Timer2 Clock Output Block Diagram

If the Timer 2 Programmable Clock Output Mode is selected, it is essential for the Port 1 control

registers, P1M1 and P1M0, to setup the P1.6 pin as an output. The accompanying diagram

illustrates the Timer2 programmable clock output timing diagram.

Timer � Clock

Timer � Overflow

P1.6/T�

FFFF

FFFE

0000

FFFF

FFFE

0000

FFFF

FFFE

0000

FFFE

0000

Timer �

Programmable Clock Output Timing Diagram – Module 0

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