HT85F2270 datasheet(107/226 Pages) HOLTEK

107 / 226 page

Rev. 1.00

107 of ��6

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Standard 8051 8-Bit Flash MCU

HT85F2260/HT85F2270/HT85F2280

Interrupt Priority

In case of simultaneous requests, the following table shows the priority that is applied. The

interrupts can be assigned into groups. Higher priority interrupts can stop the lower priority

interrupts. All interrupts are categorised into 19 groups with 4 priority levels. In cases where

both higher priority and lower priority interrupts are enabled and where a higher priority and

lower priority interrupt occurs simultaneously, the higher priority interrupt will always have

priority and will therefore be serviced first. Suitable masking of the individual interrupts using the

interrupt registers can prevent simultaneous occurrences. Each interrupt source can be individually

programmed to one of four priority levels by setting or clearing bits in the interrupt priority

registers: IP0, IP1, IP2, IP3, IP0H, IP1H, IP2H and IP3H. IP0, IP1, IP2 and IP3 hold the low order

priority bits and IP0H, IP1H, IP2H and IP3H hold the high priority bits for each interrupt.

If the priority level is the same for different groups, then an internal polling sequence determines

which interrupt request is serviced. The polling sequence is based on the vector address; an

interrupt with a lower vector address has higher priority than an interrupt with a higher vector

address. Note that the polling sequence is only used to resolve interrupt requests of the same

priority level.

Priority Levels

The accompanying table illustrates the interrupt priority level assigned by the corresponding

IPnH.x and IPn.x bits (n=0~3).

IPnH.x

IPn.x

Priority Level

Note

Level �

Highest Priorit�

Level �

↓

Level 1

↓

Level 0

Lowest Priorit�

If the interrupt levels are assigned the same priority level by the IPnH.x and IPn.x bits, the interrupt

priority is followed by the accompanying table.

HT85F2270 bảng dữ liệu(PDF) 107 Page - Holtek Semiconductor Inc