HT85F2270 datasheet(102/226 Pages) HOLTEK

102 / 226 page

Rev. 1.00

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Standard 8051 8-Bit Flash MCU

HT85F2260/HT85F2270/HT85F2280

SPSTA Register

SFR Address: E1h

Bit

Name

SPIF

WCOL

SSERR

�ODF

—

R/W

—

POR

—

Bit 7

SPIF: SPI Transmit/Receive Complete flag

0: Data is being transferred

1: SPI data transmission completed

The SPIF bit is the Transmit/Receive Complete flag and is set high automatically when

an SPI data transmission is completed, it must be cleared using the application program.

The SPIF bit can be also cleared by hardware when the data transfer is in progress. It

can also be used to generate an interrupt.

Bit 6

WCOL: SPI Write Collision flag

0: No collision

1: Collision

The WCOL flag is used to detect if a data collision has occurred. If this bit is high it

means that data has been attempted to be written to the SPDAT register during a data

transfer operation. An SPI interrupt will occur if the SPI interrupt function is enabled.

This write operation will be ignored if data is being transferred. It must be cleared using

the application program.

Bit 5

SSERR: Synchronous Serial Slave Error Flag

0: No error

1: Error

This bit is set by hardware when the SSN pin input is selected to disable the Slave

device status while the receive sequence is incomplete. A SPI interrupt will occur if the

SPI interrupt function is enabled. This bit will be cleared by disabling the SPI module,

clearing the SPEN bit in the SPCON register.

Bit 4

MODF: SPI Master/Slave Mode Mismatch Flag

0: No Mismatch

1: Mismatch

This bit is set by hardware when the Slave Select SSN pin level conflicts with actual

Master/Slave mode of the SPI Master controller which is configured as a master while

externally selected as a slave. A SPI interrupt will occur if the SPI interrupt function is

enabled. It must be cleared using the application program.

Bit 3~0

Unimplemented, read as "0"

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