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STM32F303RC bảng dữ liệu(PDF) 105 Page - STMicroelectronics

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STM32F302xx/STM32F303xx
Electrical characteristics
Doc ID 023353 Rev 5
105/133
6.3.18
ADC characteristics
Unless otherwise specified, the parameters given in Table 66 to Table 69 are guaranteed by
design, with conditions summarized in Table 22.
Table 66.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage for
ADC
2-
3.6
V
fADC
ADC clock frequency
0.14
-
72
MHz
fS
(1)
Sampling rate
Resolution = 12 bits,
Fast Channel
0.01
-
5.14
MSPS
Resolution = 10 bits,
Fast Channel
0.012
-
6
Resolution = 8 bits,
Fast Channel
0.014
-
7.2
Resolution = 6 bits,
Fast Channel
0.0175
-
9
fTRIG
(1)
External trigger frequency
fADC = 72 MHz
Resolution = 12 bits
-
-
5.14
MHz
Resolution = 12 bits
-
-
14
1/fADC
VAIN
Conversion voltage range
0
-
VDDA
V
RAIN
(1)
External input impedance
-
-
100
k
Ω
CADC
(1)
Internal sample and hold
capacitor
-5
-
pF
tCAL
(1)
Calibration time
fADC = 72 MHz
1.56
µs
112
1/fADC
tlatr
(1)
Trigger conversion latency
Regular and injected
channels without conversion
abort
CKMODE = 00
1.5
2
2.5
1/fADC
CKMODE = 01
-
-
2
1/fADC
CKMODE = 10
-
-
2.25
1/fADC
CKMODE = 11
-
-
2.125
1/fADC
tlatrinj
(1)
Trigger conversion latency
Injected channels aborting a
regular conversion
CKMODE = 00
2.5
3
3.5
1/fADC
CKMODE = 01
-
-
3
1/fADC
CKMODE = 10
-
-
3.25
1/fADC
CKMODE = 11
-
-
3.125
1/fADC
tS
(1)
Sampling time
fADC = 72 MHz
0.021
-
8.35
µs
1.5
-
601.5
1/fADC
TADCVREG
_STUP
(1)
ADC Voltage Regulator
Start-up time
-
-
10
µs
tCONV
(1)
Total conversion time
(including sampling time)
fADC = 72 MHz
Resolution = 12 bits
0.19
-
3.5
µs
Resolution = 12 bits
14 to 252 (tS for sampling + 12.5 for
successive approximation)
1/fADC
1.
Data guaranteed by design



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