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WM8948ECS/R bảng dữ liệu(PDF) 108 Page - Wolfson Microelectronics plc

tên linh kiện WM8948ECS/R
Giải thích chi tiết về linh kiện  Stereo Low-Power CODEC with Video Buffer and Touch Panel Controller
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WM8948
Production Data
w
PD, May 2011, Rev 4.1
108
In Read operations (R/W=1), the SDATA pin is ignored following receipt of the valid register address.
SDOUT is driven by the WM8948.
The 4-wire control mode timing is illustrated in Figure 47 and Figure 48.
Figure 47 4-Wire Readback (CMOS)
Figure 48 4-Wire Readback (Open Drain)
POWER MANAGEMENT
The WM8948 has two control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To minimise pop or click noise,
it is important to enable or disable these functions in the correct order, and to use the signal mute
registers as part of a carefully structured control sequence. Refer to the “Recommended Power
Up/Down Sequence” section for more details.
The power management control registers are described in Table 69.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2 (02h)
Power
management
1
13
INPPGAR_ENA
0
Right Input PGA Enable
0 = Disabled
1 = Enabled
12
INPPGAL_ENA
0
Left Input PGA Enable
0 = Disabled
1 = Enabled



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