HT67F60 datasheet(174/242 Pages) HOLTEK

174 / 242 page

Rev. 1.50

174

March 06 , 2012

Rev. 1.50

175

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it

means that a acknowledge signal has been received at the 9th clock, after 8 bits of data

have been transmitted. When the slave device in the transmit mode, the slave device

checks the RXAK flag to determine if the master receiver wishes to receive the next

byte. The slave transmitter will therefore continue sending out data until the RXAK

flag is "1". When this occurs, the slave transmitter will release the SDA line to allow

the master to send a STOP signal to release the I2C Bus.

The SIMD register is used to store the data being transmitted and received. The same

SPI bus, the actual data to be transmitted must be placed in the SIMD register. After

the data is received from the SPI bus, the device can read it from the SIMD register.

Any transmission or reception of data from the SPI bus must be made via the SIMD

●

SIMD Register

Bit

Name

R/W

POR

"X" unknown

●

SIMA Register

Bit

Name

IICA6

IICA5

IICA4

IICA3

IICA2

IICA1

IICA0

—

R/W

—

POR

—

"X" unknown

Bit 7~1

IICA6~ IICA0: I2C slave address

IICA6~ IICA0 is the I2C slave address bit 6~ bit 0.

The SIMA register is also used by the SPI interface but has the name SIMC2. The

SIMA register is the location where the 7-bit slave address of the slave device is

stored. Bits 7~ 1 of the SIMA register define the device slave address. Bit 0 is not

defined.

When a master device, which is connected to the I2C bus, sends out an address, which

matches the slave address in the SIMA register, the slave device will be selected. Note

that the SIMA register is the same register address as SIMC2 which is used by the SPI

interface.

Bit 0

Undefined bit

This bit can be read or written by user software program.

I 2 C Da ta R eg is te r

(S IM D)

Sl av e Ad dr e ss Re gi st er

(S IM A)

Sh i ft R egi st er

Di re ct i on Co nt ro l

A ddr e ss Ma tc h

HA AS B it

I 2 C In te rr up t

Da ta i n LS B

Da ta O ut M SB

Tr ans mi t/R ec ei ve

C ont ro l Un it

8- bi t D at a Co mp le te

De te c t S ta rt o r St op

Da ta B us

A ddr es s

Co mp ar at or

E nabl e/ Di s abl e A ck now le dge

R ead/ wr it e Sl av e

SR W Bi t

HB B Bi t

HT X Bi t

SC L Pi n

SD A Pi n

HC F Bi t

I2C Block Diagram

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