HT67F60 datasheet(156/242 Pages) HOLTEK

156 / 242 page

Rev. 1.50

156

March 06 , 2012

Rev. 1.50

157

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

Summary of A/D Conversion Steps

The following summarises the individual steps that should be executed in order to implement an A/

D conversion process.

● Step 1

Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the

ADCR1 register.

● Step 2

Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero.

● Step 3

Select which channel is to be connected to the internal A/D converter by correctly programming

the ACS4~ACS0 bits which are also contained in the ADCR1 and ADCR0 register.

● Step 4

Select which pins are to be used as A/D inputs and configure them by correctly programming the

ACE11~ACE0 bits in the ACERH and ACERL registers.

● Step 5

If the interrupts are to be used, the interrupt control registers must be correctly configured to

ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and

the A/D converter interrupt bit, EADI, must both be set high to do this.

● Step 6

The analog to digital conversion process can now be initialised by setting the START bit in the

ADCR register from low to high and then low again. Note that this bit should have been originally

cleared to zero.

● Step 7

To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0

occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an

alternative method, if the interrupts are enabled and the stack is not full, the program can wait for

an A/D interrupt to occur.

Note: When checking for the end of the conversion process, if the method of polling the EOCB bit

in the ADCR0 register is used, the interrupt enable step above can be omitted.

t AD C

A/ D c onv er si on ti me

00011B

00010B

ST AR T

EO CB

AC S4 ~A CS 0

Po we r- on

Re se t

E nd of A /D

c onv er si on

1: D ef i ne por t c on fi gur at io n

2: S el ec t anal og ch a nnel

St ar t of A /D

c onv er si on

Re se t A/ D

c onv er te r

A/ D sa mp li ng t im e

t AD S

00000B

St ar t o f A /D

c onv er si on

Re se t A/ D

c onv er te r

00001B

St ar t o f A /D

c onv er si on

Re se t A/ D

c onv er te r

E nd of A /D

c onv er si on

A/ D sa mp li ng t im e

t AD S

of f

t ON 2S T

t AD C

A/ D c onv er si on ti me

of f

AD OF F

AD C M odul e

A/D Conversion Timing

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