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MPC5673K bảng dữ liệu(PDF) 123 Page - Freescale Semiconductor, Inc |
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MPC5673K bảng dữ liệu(HTML) 123 Page - Freescale Semiconductor, Inc |
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123 / 140 page ![]() Electrical characteristics MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor 123 3.22.8 Fast ethernet interface MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible. They follow the CMOS electrical characteristics. 3.22.8.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK) The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency. 2tPDI_IS SR Input setup time1 —3 — ns 3tPDI_IH SR Input hold time1 —3 — ns NOTES: 1 Data can be captured at both launching and capturing edge of PDI_CLK. PDI timing Table 69. MII receive signal timing No. Parameter Min Max Unit 1 RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5— ns 2 RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5— ns 3 RX_CLK pulse width high 40% 60% RX_CLK period 4 RX_CLK pulse width low 40% 60% RX_CLK period Table 68. PDI electrical characteristics (continued) No. Symbol Parameter Conditions Min Max Unit PDI_CLOCK 2 3 PDI_DATA[15:0] Input Data Valid PDI_LINE_V PDI_FRAME_V 1 |
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