L6460 datasheet(109/139 Pages) STMICROELECTRONICS

109 / 139 page

L6460

GPIO pins

Doc ID 17713 Rev 1

109/139

22.6

GPIO[5]

The GPIO[5] truth table is (for the abbreviation list please refer to Table 40).

Table 46.

GPIO[5] truth table

Master(1)

Master bit is at logic level “1” when

L6460 is used as a master device (seeChapter 8)

AUX1

system

and

Vloop1

external(2)

This bit is at logic level “1” if AUX1 regulator is a system regulator but its power stage is externally realized

(and therefore the regulation loop is not used to drive bridge 3). In this case Vloop1IsSys bit will be at logic

level “1”, while Vloop1OnMtr3SideA and Vloop1OnMtr3SideB bits will be at logic level “0” in

CoreConfigReg register.

GPIO[5] SPI BITS

Function

Note

GpioOut

enable[5]

Mode[2]

Mode[1]

Mode[0]

Slave control

Reg Loop1 OUT

(3)

In all configurations in which GPIO[5] is enabled as output:

a) the GPIO[5] pin can be always used as an analog input to the ADC system (ADC function) by writing its

address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;

b) the GPIO[5] pin can be always used as a digital input so its value can be always read through SPI

interface (SPI_IN function);

the GPIO[5] pin is a rail to rail, back to back output supplied by V3v3.

HiZ (SPI_IN)

SPI OUT

(3)

Comp1OUT

(3)

Reg Loop1 OUT

(3)

AuxPwm3

(3)

SPI OUT inverted

(3)

Comp1OUT inverted

(3)

Reg Loop1 OUT

inverted

(3)

AuxPwm3 inverted

(3)

L6460 bảng dữ liệu(PDF) 109 Page - STMicroelectronics

L6460 bảng dữ liệu(HTML) 109 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL