ST10F272Z2T3 datasheet(178/189 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F272Z2

178/189

25.8.18

CLKOUT and READY

VDD = 5 V ± 10%, VSS = 0 V, TA = -40 to + 125 °C, CL = 50 pF

These timings are given for characterization purposes only, in order to assure recognition at a specific

clock edge.

Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.

This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle, tF refers

to the current bus cycle.

Table 81.

CLKOUT and READY timings

Symbol

Parameter

FCPU = 40 MHz

TCL = 12.5 ns

Variable CPU Clock

1/2 TCL = 1 to 64 MHz

min.

max.

min.

max.

t29

CLKOUT cycle time

2TCL

t30

CLKOUT high time

–

TCL – 3.5

–

t31

CLKOUT low time

–

TCL – 2.5

–

t32

CLKOUT rise time

–

t33

CLKOUT fall time

–

t34

CLKOUT rising edge to

ALE falling edge

– 2 + tA

8 + tA

– 2 + tA

8 + tA

t35

Synchronous READY

setup time to CLKOUT

–

t36

Synchronous READY

hold time after CLKOUT

2–

–

t37

Asynchronous READY

low time

–

2TCL + 10

–

t58

Asynchronous READY

setup time 1

–

t59

Asynchronous READY

hold time 1

2–

–

t60

Async. READY hold time after

RD, WR high (Demultiplexed

Bus) 2

02tA + tC + tF

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