ST10F272Z2T3 datasheet(133/189 Pages) STMICROELECTRONICS

tên linh kiện	ST10F272Z2T3

Giải thích chi tiết về linh kiện	16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

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ST10F272Z2

Known limitations

133/189

24.4

Spurious BREQ pulse in slave mode during external bus

arbitration phase

Description

Sporadic bus errors may occur when external bus arbitration is used via the HOLD function

and the ST10F272Z2 is configured as a slave.

After the slave has been granted access to the bus, the slave disables the BREQ signal

sporadically for a short time, even though slave access to the bus has not been completed.

The master starts then its own bus access, generating a bus conflict between master and

slave.

Workaround

To avoid producing any spurious BREQ pulse during a slave external bus arbitration phase,

it is necessary to guarantee that the time between the HLDA assertion (Bus Acknowledge

from Master device) and the following HOLD falling edge (Bus Request from Master) is

longer than three clock cycles.

This can be implemented by delaying the HOLD signal with an RC circuit as shown in Figure

Figure 39.

ST10 in Slave mode

BREQ

HLDA

HOLD

BREQ (P6.7)

HLDA (P6.6)

HOLD (P6.5)

Master

ST10 in Slave mode

VSS

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