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PIC18F23K22-E/ML bảng dữ liệu(PDF) 460 Page - Microchip Technology |
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PIC18F23K22-E/ML bảng dữ liệu(HTML) 460 Page - Microchip Technology |
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460 / 496 page ![]() PIC18(L)F2X/4XK22 DS41412C-page 460 Preliminary 2010 Microchip Technology Inc. TABLE 27-24: A/D CONVERSION REQUIREMENTS Param. No. Symbol Characteristic Min Max Units Conditions 130 TAD A/D Clock Period 0.7 25.0(1) sTOSC based, -40 C to +85C 0.7 4.0(1) sTOSC based, +85 C to +125C 1.0 4.0 s FRC mode, VDD 2.0V 131 TCNV Conversion Time (not including acquisition time) (Note 2) 12 12 TAD 132 TACQ Acquisition Time (Note 3) 1.4 — sVDD = 3V, Rs = 50 135 TSWC Switching Time from Convert Sample — (Note 4) 136 TDIS Discharge Time 2 2 TAD Legend: TBD = To Be Determined Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES register may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50 . 4: On the following cycle of the device clock. |
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