PIC16F1825-ESLASHML datasheet(101/420 Pages) MICROCHIP

101 / 420 page

 2010 Microchip Technology Inc.

Preliminary

DS41440A-page 101

PIC16F/LF1825/1829

8.5.9

PIR4 REGISTER(1)

The PIR4 register contains the interrupt flag bits, as

shown in Register 8-9.

Note 1: The PIR4 register is available only on the

PIC16F/LF1829 device.

2: Interrupt flag bits are set when an inter-

rupt condition occurs, regardless of the

state of its corresponding enable bit or

the Global Enable bit, GIE, of the

INTCON register. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4(1)

U-0

R/W/HS-0/0 R/W/HS-0/0

—

BCL2IF

SSP2IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HS = Bit is set by hardware

bit 7-6

Unimplemented: Read as ‘0’

bit 1

BCL2IF: MSSP2 Bus Collision Interrupt Flag bit

1 = A Bus Collision was detected (must be cleared in software)

0 = No Bus collision was detected

bit 0

SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit

1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)

0 = Waiting to Transmit/Receive/Bus Condition in progress

Note 1:

This register is only available on PIC16F/LF1829.

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