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SPMCK16Z4MPV20 bảng dữ liệu(PDF) 321 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV20 bảng dữ liệu(HTML) 321 Page - Freescale Semiconductor, Inc |
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321 / 500 page  M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER’S MANUAL A-37 Table A-19 Low Voltage 16.78-MHz Background Debug Mode Timing (V DD and V DDSYN = 2.7 to 3.6Vdc, V SS = 0 Vdc, T A = T L to T H) 1 NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. Num Characteristic Symbol Min Max Unit B0 DSI Input Setup Time tDSISU 15 — ns B1 DSI Input Hold Time tDSIH 15 — ns B2 DSCLK Setup Time tDSCSU 15 — ns B3 DSCLK Hold Time tDSCH 15 — ns B4 DSO Delay Time tDSOD —35 ns B5 DSCLK Cycle Time tDSCCYC 2— tcyc B6 CLKOUT High to FREEZE Asserted/Negated tFRZAN —50 ns B7 CLKOUT High to IPIPE1 High Impedance tIFZ —50 ns B8 CLKOUT High to IPIPE1 Valid tIF —50 ns B9 DSCLK Low Time tDSCLO 1— tcyc B10 IPIPE1 High Impedance to FREEZE Asserted tIPFA TBD — t cyc B11 FREEZE Negated to IPIPE[0:1] Active tFRIP TBD — t cyc Table A-20 16.78-MHz Background Debug Mode Timing (V DD and V DDSYN = 5.0 Vdc ± 10%, V SS = 0 Vdc, T A = T L to T H) 1 NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. Num Characteristic Symbol Min Max Unit B0 DSI Input Setup Time tDSISU 15 — ns B1 DSI Input Hold Time tDSIH 10 — ns B2 DSCLK Setup Time tDSCSU 15 — ns B3 DSCLK Hold Time tDSCH 10 — ns B4 DSO Delay Time tDSOD —25 ns B5 DSCLK Cycle Time tDSCCYC 2— tcyc B6 CLKOUT High to FREEZE Asserted/Negated tFRZAN —50 ns B7 CLKOUT High to IPIPE1 High Impedance tIFZ — TBD ns B8 CLKOUT High to IPIPE1 Valid tIF — TBD ns B9 DSCLK Low Time tDSCLO 1— tcyc B10 IPIPE1 High Impedance to FREEZE Asserted tIPFA TBD — tcyc B11 FREEZE Negated to IPIPE[0:1] Active tFRIP TBD — tcyc Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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