PC312XDP512F0CFVR datasheet(1032/1348 Pages) FREESCALE

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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

1034

Freescale Semiconductor

Figure 24-69. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)

Figure 24-70. Pulse Illustration

A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by

4 consecutive samples of an active level directly or indirectly.

The filters are continuously clocked by the bus clock in run and wait mode. In stop mode, the clock is

generated by an RC-oscillator in the port integration module. To maximize current saving the RC

oscillator runs only if the following condition is true on any pin individually:

Sample count <= 4 and interrupt enabled (PIE = 1) and interrupt flag not set (PIF = 0).

24.0.9

Low-Power Options

24.0.9.1

Run Mode

No low-power options exist for this module in run mode.

Table 24-62. Pulse Detection Criteria

Pulse

Mode

STOP

Unit

STOP1

1. These values include the spread of the oscillator frequency over

temperature, voltage and process.

Ignored

tpulse ≤ 3

Bus clocks

tpulse ≤ tpign

Uncertain

3 < tpulse < 4

Bus clocks

tpign < tpulse < tpval

Valid

tpulse ≥ 4

Bus clocks

tpulse ≥ tpval

Glitch, ﬁltered out, no interrupt ﬂag set

Valid pulse, interrupt ﬂag set

tpign

tpval

uncertain

tpulse

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