PC312XDP512F0CFVR datasheet(518/1348 Pages) FREESCALE

518 / 1348 page

Chapter 12 Serial Peripheral Interface (S12SPIV4)

MC9S12XDP512 Data Sheet, Rev. 2.21

518

Freescale Semiconductor

12.2.3

SS — Slave Select Pin

This pin is used to output the select signal from the SPI module to another peripheral with which a data

transfer is to take place when it is conﬁgured as a master and it is used as an input to receive the slave select

signal when the SPI is conﬁgured as slave.

12.2.4

SCK — Serial Clock Pin

In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.

12.3

Memory Map and Register Deﬁnition

This section provides a detailed description of address space and registers used by the SPI.

12.3.1

Module Memory Map

The memory map for the SPI is given in Figure 12-2. The address listed for each register is the sum of a

base address and an address offset. The base address is deﬁned at the SoC level and the address offset is

deﬁned at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have

no effect.

Name

Bit 7

Bit 0

SPICR1

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

SPICR2

MODFEN

BIDIROE

SPISWAI

SPC0

SPIBR

SPPR2

SPPR1

SPPR0

SPR2

SPR1

SPR0

SPISR

SPIF

SPTEF

MODF

0000

Reserved

SPIDR

Bit 7

Bit 0

Reserved

= Unimplemented or Reserved

Figure 12-2. SPI Register Summary

PC312XDP512F0CFVR bảng dữ liệu(PDF) 518 Page - Freescale Semiconductor, Inc

PC312XDP512F0CFVR bảng dữ liệu(HTML) 518 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL