PC312XDP512F0CFVR datasheet(453/1348 Pages) FREESCALE

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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

453

10.3.3.2

Data Segment Registers (DSR0-7)

The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.

The number of bytes to be transmitted or received is determined by the data length code in the

corresponding DLR register.

Table 10-30. IDR1 Register Field Descriptions

Field

Description

7:5

ID[2:0]

Standard Format Identiﬁer — The identiﬁers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number. See also ID bits in Table 10-29.

RTR

Remote Transmission Request — This ﬂag reﬂects the status of the Remote Transmission Request bit in the

CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the

transmission of an answering frame in software. In the case of a transmit buffer, this ﬂag deﬁnes the setting of

the RTR bit to be sent.

0 Data frame

1 Remote frame

IDE

ID Extended — This ﬂag indicates whether the extended or standard identiﬁer format is applied in this buffer. In

the case of a receive buffer, the ﬂag is set as received and indicates to the CPU how to process the buffer

identiﬁer registers. In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send.

0 Standard format (11 bit)

1 Extended format (29 bit)

76543210

Reset:

xxxxxxxx

= Unused; always read ‘x’

Figure 10-32. Identiﬁer Register 2 — Standard Mapping

76543210

Reset:

xxxxxxxx

= Unused; always read ‘x’

Figure 10-33. Identiﬁer Register 3 — Standard Mapping

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