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PIC16F685-E/ML bảng dữ liệu(PDF) 135 Page - Microchip Technology |
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PIC16F685-E/ML bảng dữ liệu(HTML) 135 Page - Microchip Technology |
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135 / 306 page ![]() © 2008 Microchip Technology Inc. DS41262E-page 133 PIC16F631/677/685/687/689/690 FIGURE 11-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE TABLE 11-4: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES CCPR1L CCPR1H (Slave) Comparator TMR2 Comparator PR2 (1) RQ S Duty Cycle Registers DC1B<1:0> Clear Timer2, toggle PWM pin and latch duty cycle Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. TRIS CCP1/P1A TRIS P1B TRIS P1C TRIS P1D Output Controller P1M<1:0> 2 CCP1M<3:0> 4 PWM1CON CCP1/P1A P1B P1C P1D Note 1: The TRIS register value for each PWM output must be configured appropriately. 2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Pulse Steering enables outputs in Single mode. |
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