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PIC16F688-I/ML bảng dữ liệu(PDF) 151 Page - Microchip Technology |
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PIC16F688-I/ML bảng dữ liệu(HTML) 151 Page - Microchip Technology |
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151 / 204 page ![]() © 2009 Microchip Technology Inc. DS41203E-page 149 PIC16F688 14.5 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions VIL Input Low Voltage I/O Port: D030 with TTL buffer Vss — 0.8 V 4.5V ≤ VDD ≤ 5.5V D030A Vss — 0.15 VDD V2.0V ≤ VDD ≤ 4.5V D031 with Schmitt Trigger buffer Vss — 0.2 VDD V2.0V ≤ VDD ≤ 5.5V D032 MCLR, OSC1 (RC mode)(1) VSS —0.2 VDD V D033 OSC1 (XT and LP modes) VSS —0.3 V D033A OSC1 (HS mode) VSS —0.3 VDD V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V4.5V ≤ VDD ≤ 5.5V D040A 0.25 VDD + 0.8 — VDD V2.0V ≤ VDD ≤ 4.5V D041 with Schmitt Trigger buffer 0.8 VDD —VDD V2.0V ≤ VDD ≤ 5.5V D042 MCLR 0.8 VDD —VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V D043A OSC1 (HS mode) 0.7 VDD —VDD V D043B OSC1 (RC mode) 0.9 VDD —VDD V (Note 1) IIL Input Leakage Current(2) D060 I/O ports — ± 0.1 ± 1 μAVSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR(3) — ± 0.1 ± 5 μAVSS ≤ VPIN ≤ VDD D063 OSC1 — ± 0.1 ± 5 μAVSS ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration D070* IPUR PORTA Weak Pull-up Current 50 250 400 μAVDD = 5.0V, VPIN = VSS VOL Output Low Voltage(5) D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.) VOH Output High Voltage(5) D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.) * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 9.0 “Data EEPROM and Flash Program Memory Control” for additional information. 5: Including OSC2 in CLKOUT mode. |
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