EM357-RTR datasheet(203/240 Pages) ETC2

203 / 240 page

EM351 / EM357

Figure 11-1. Peripheral Interrupts Block Diagram

latch

read

latch

write 1

read

AND

write 1

latch

write 1

interrupts into NVIC/CPU

INT_PENDSET

INT_PENDCLR

INT_CFGSET

INT_CFGCLR

INT_MISS

source interrupt events

latch

write 1

read

AND

INT_periphCFG

INT_periphFLAG

read

write 1

peripheral interrupt instance

interrupts from all peripherals

AND

Given a peripheral, ‘periph’, the Event Manager registers (INT_periphCFG and INT_periphFLAG) follow the

form:

INT_periphCFG enables and disables second-level interrupts. Writing 1 to a bit in the INT_periphCFG

The INT_periphCFG register behaves like a mask, and is responsible for allowing the INT_periphFLAG bits

to propagate into the top-level NVIC interrupts.

INT_periphFLAG indicates second-level interrupts that have occurred. Writing 1 to a bit in a

INT_periphFLAG register clears the second-level interrupt. Writing 0 to any bit in the INT_periphFLAG

meaning if any second-level interrupt occurs, then the corresponding bit in the INT_periphFLAG register is

set regardless of the state of INT_periphCFG.

If a bit in the INT_periphCFG register is set after the corresponding bit in the INT_periphFLAG register is set

then the second-level interrupt propagates into the top-level interrupts. The interrupt flags (signals) from the

second-level interrupts into the top-level interrupts are level-sensitive. If a top-level NVIC interrupt is driven

by a second-level EM interrupt, then the top-level NVIC interrupt cannot be cleared until all second-level EM

interrupts are cleared.

The INT_periphFLAG register bits are designed to remain set if the second-level interrupt event re-occurs at

the same moment as the INT_periphFLAG register bit is being cleared. This ensures the re-occurring second-

level interrupt event is not missed.

If another enabled second-level interrupt event of the same type occurs before the first interrupt event is

cleared, the second interrupt event is lost because no counting or queuing is used. However, this condition is

detected and stored in the top-level INT_MISS register to facilitate software detection of such problems. The

INT_MISS register is “acknowledged” in the same way as the INT_periphFLAG register—by writing a 1 into the

corresponding bit to be cleared.

Table 11-2 provides a map of all peripheral interrupts. This map lists the top-level NVIC Interrupt bits and, if

there is one, the corresponding second-level EM Interrupt register bits that feed the top-level interrupts.

11-4

120-035X-000D

Preliminary

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