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MPC8548E bảng dữ liệu(PDF) 125 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8548E
Giải thích chi tiết về linh kiện  PowerQUICC??III Integrated Processor Hardware Specifications
PDF  144 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC8548E bảng dữ liệu(HTML) 125 Page - Freescale Semiconductor, Inc

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MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
125
Clocking
19.2
CCB/SYSCLK PLL Ratio
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform
clock. The frequency of the CCB is set using the following reset signals, as shown in Table 77:
•
SYSCLK input signal
•
Binary value on LA[28:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB
frequency must equal the DDR data rate.
For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.
Table 76. Memory Bus Clocking Specifications (MPC8543E)
Characteristic
Maximum Processor Core Frequency
Unit
Notes
800, 1000 MHz
Min
Max
Memory bus clock speed
166
200
MHz
1, 2
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio
settings.
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
Table 77. CCB Clock Ratio
Binary Value of LA[28:31] Signals
CCB:SYSCLK Ratio
Binary Value of LA[28:31] Signals
CCB:SYSCLK Ratio
0000
16:1
1000
8:1
0001
Reserved
1001
9:1
0010
2:1
1010
10:1
0011
3:1
1011
Reserved
0100
4:1
1100
12:1
0101
5:1
1101
20:1
0110
6:1
1110
Reserved
0111
Reserved
1111
Reserved



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