ADE5166 datasheet(146/156 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Rev. B | Page 146 of 156

I2C RECEIVE AND TRANSMIT FIFOS

The I2C peripheral has a 4-byte receive FIFO and a 4-byte transmit

FIFO. The buffers reduce the overhead associated with using

the I2C peripheral. Figure 116 shows the operation of the I2C

receive and transmit FIFOs.

The Tx FIFO buffer can be loaded with four bytes to be transmitted

to the slave at the beginning of a write operation. When the trans-

mit FIFO is empty, the I2C transmit interrupt flag (I2CTxIRQ) is

set in the I2C interrupt status SFR (SPI2CSTAT, Address 0xEA[4]),

and the PC vectors to the I2C interrupt vector if this interrupt is

enabled. If a new byte is not loaded into the Tx FIFO before it is

needed in the transmit shift register, the communication stops.

An error, such as not receiving an acknowledgement, also causes

the communication to terminate. In case of an error during a

write operation, the Tx FIFO is flushed.

The Rx FIFO buffer allows four bytes to be read in from the slave

before the MCU has to read the data. A receive interrupt can be

gener-ated after each byte is received or when the Rx FIFO is

full. If the peripheral is reading from a slave address, the communi-

cation stops when the number of received bytes equals the number

set in the I2CRCT bits in the I2CMOD SFR (Address 0xE8[4:0]).

An error, such as not receiving an acknowledgement, also causes

the communication to terminate.

I2CTx

4-BYTE FIFO

MOV I2CTx, TxDATA1

MOV I2CTx, TxDATA2

MOV I2CTx, TxDATA3

MOV I2CTx, TxDATA4

CODE TO FILL Tx FIFO:

TRANSMIT SHIFT REGISTER

I2CRx

RECEIVE SHIFT REGISTER

4-BYTE FIFO

CODE TO READ Rx FIFO:

MOV A, I2CRx; RESULT: A = RxDATA1

MOV A, I2CRx; RESULT: A = RxDATA2

MOV A, I2CRx; RESULT: A = RxDATA3

MOV A, I2CRx; RESULT: A = RxDATA4

TxDATA1

TxDATA2

TxDATA3

TxDATA4

RxDATA4

RxDATA3

RxDATA2

RxDATA1

Figure 116. I2C FIFO Operation

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