ATmega328P datasheet(251/448 Pages) ATMEL

251 / 448 page

251

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

Figure 23-1. Analog to Digital Converter Block Schematic Operation,

The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input

pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended

inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Volt-

age reference and input channel selections will not go into effect until ADEN is set. The ADC

does not consume power when ADEN is cleared, so it is recommended to switch off the ADC

before entering power saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data

Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers

is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL. & STATUS

ADC DATA REGISTER

(ADCH/ADCL)

CONVERSION LOGIC

10-BIT DAC

SAMPLE & HOLD

COMPARATOR

INTERNAL 1.1V

REFERENCE

MUX DECODER

AVCC

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

ADC MULTIPLEXER

OUTPUT

AREF

BANDGAP

REFERENCE

PRESCALER

GND

INPUT

MUX

TEMPERATURE

SENSOR

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