ATmega16A datasheet(151/352 Pages) ATMEL

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8154B–AVR–07/09

ATmega16A

Figure 19-3. Synchronous Mode XCK Timing.

The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is

used for data change. As Figure 19-3 shows, when UCPOL is zero the data will be changed at

rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at

falling XCK edge and sampled at rising XCK edge.

19.4

Frame Formats

A serial frame is defined to be one character of data bits with synchronization bits (start and stop

bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of

the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit. Then the next data bits,

up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit

is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can

be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Figure 19-4 illustrates the possible combinations of the frame formats. Bits inside brackets are

optional.

Figure 19-4. Frame Formats

Start bit, always low.

(n)

Data bits (0 to 8).

Parity bit. Can be odd or even.

Stop bit, always high.

IDLE

No transfers on the communication line (RxD or TxD). An IDLE line must

high.

RxD / TxD

XCK

RxD / TxD

XCK

UCPOL = 0

UCPOL = 1

Sample

[5]

[6]

[7]

[8]

[P]

Sp1 [Sp2]

(St / IDLE)

(IDLE)

FRAME

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