ATmega16A datasheet(117/352 Pages) ATMEL

117 / 352 page

117

8154B–AVR–07/09

ATmega16A

17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation

17.1

Features

• Single Compare unit Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)

• Allows clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

17.2

Overview

Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simpli-

fied block diagram of the 8-bit Timer/Counter is shown in Figure 17-1. For the actual placement

of I/O pins, refer to “Pinout ATmega16A” on page 2. CPU accessible I/O Registers, including I/O

bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed

in the “Register Description” on page 130.

Figure 17-1. 8-bit Timer/Counter Block Diagram

17.2.1

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt

request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR).

All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and

TIMSK are not shown in the figure since these registers are shared by other timer units.

Timer/Counter

TCNTn

Waveform

Generation

OCn

= 0

Control Logic

= 0xFF

TOP

BOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCn

(Int.Req.)

Synchronization Unit

OCRn

TCCRn

ASSRn

Status flags

clk

I/O

clk

ASY

Synchronized Status flags

asynchronous mode

select (ASn)

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clk

I/O

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