ATmega325P datasheet(218/364 Pages) ATMEL

218 / 364 page

218

8023F–AVR–07/09

ATmega325P/3250P

21.9

21.9.1

ADMUX – ADC Multiplexer Selection Register

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 6. If these bits are

changed during a conversion, the change will not go in effect until this conversion is complete

(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external

reference voltage is being applied to the AREF pin.

•

Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a complete description of this bit, see ”ADCL and ADCH – The ADC Data Register” on

page 221.

• Bits 4:0 – MUX4:0: Analog Channel Selection Bits

The value of these bits selects which combination of analog inputs are connected to the ADC.

See Table 21-3 on page 219 for details. If these bits are changed during a conversion, the

change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).

Bit

765

4321

(0x7C)

REFS1

REFS0

ADLAR

MUX4

MUX3

MUX2

MUX1

MUX0

ADMUX

Read/Write

R/W

Initial Value

000

0000

Table 6. Voltage Reference Selections for ADC

REFS1

REFS0

Voltage Reference Selection

AREF, Internal Vref turned off

AVCC with external capacitor at AREF pin

Reserved

Internal 1.1V Voltage Reference with external capacitor at AREF pin

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