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ATtiny88 bảng dữ liệu(PDF) 174 Page - ATMEL Corporation |
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ATtiny88 bảng dữ liệu(HTML) 174 Page - ATMEL Corporation |
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174 / 266 page ![]() 174 8008C–AVR–03/09 ATtiny48/88 trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set . 17.13.5 DIDR0 – Digital Input Disable Register 0 • Bit 7:0 – ADC7D..ADC0D: ADC7..0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis- abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. Table 17-6. ADC Auto Trigger Source Selections ADTS2 ADTS1 ADTS0 Trigger Source 0 0 0 Free Running mode 0 0 1 Analog Comparator 0 1 0 External Interrupt Request 0 0 1 1 Timer/Counter0 Compare Match A 1 0 0 Timer/Counter0 Overflow 1 0 1 Timer/Counter1 Compare Match B 1 1 0 Timer/Counter1 Overflow 1 1 1 Timer/Counter1 Capture Event Bit 7 65 43 21 0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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