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ATtiny88 bảng dữ liệu(PDF) 128 Page - ATMEL Corporation |
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ATtiny88 bảng dữ liệu(HTML) 128 Page - ATMEL Corporation |
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128 / 266 page ![]() 128 8008C–AVR–03/09 ATtiny48/88 Figure 15-6. Typical Data Transmission 15.4 Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately switch to Slave mode to check whether it is being addressed by the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. • Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process. Figure 15-7. SCL Synchronization Between Multiple Masters 12 7 8 9 Data Byte Data MSB Data LSB ACK SDA SCL START 12 789 Addr MSB Addr LSB R/W ACK SLA+R/W STOP TA low TA high SCL from Master A SCL from Master B SCL Bus Line TB low TB high Masters Start Counting Low Period Masters Start Counting High Period |
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