ATmega32U2 datasheet(177/314 Pages) ATMEL

177 / 314 page

177

7799B–AVR–07/09

ATmega8U2/16U2/32U2

Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD

Baud rate (in bits per second, bps)

OSC

System Oscillator clock frequency

UBRRn

Contents of the UBRRnH and UBRRnL Registers, (0-4095)

19.4

SPI Data Modes and Timing

There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which

are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are

shown in Figure 19-1. Data bits are shifted out and latched in on opposite edges of the XCKn

signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-

ality is summarized in Table 19-2. Note that changing the setting of any of these bits will corrupt

all ongoing communication for both the Receiver and Transmitter.

Figure 19-1. UCPHAn and UCPOLn data transfer timing diagrams.

Table 19-1.

Equations for Calculating Baud Rate Register Setting

Operating Mode

Equation for Calculating Baud Rate(1)

Equation for Calculating UBRRn Value

Synchronous Master mode

BAUD

OSC

2 UBRRn

()

---------------------------------------

UBRRn

OSC

2BAUD

--------------------

–

Table 19-2.

UCPOLn and UCPHAn Functionality-

UCPOLn

UCPHAn

SPI Mode

Leading Edge

Trailing Edge

Sample (Rising)

Setup (Falling)

Setup (Rising)

Sample (Falling)

Setup (Rising)

Setup (Falling)

Sample (Rising)

XCK

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

UCPOL=0

UCPOL=1

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