R5F64112DFB datasheet(102/105 Pages) RENESAS

102 / 105 page

A- 3

• Completed “under development” phase of part numbers

R5F64110DFB, R5F64111DFB, R5F64112DFB, R5F64114DFB,

R5F64115DFB, and R5F64116DFB in Table 1.7

• Added product information for 100-pin LGA and 80-/64-pin packages

to Table 1.7

• Added product information for 100-pin LGA and 80-/64-pin packages,

and 32-Kbyte RAM to Figure 1.1

• Deleted hyphenation for part number in Figure 1.1

11, 12,

14, 18,

• Added Figures 1.3, 1.4, and 1.6 to 1.8 to provide block diagrams and

pin assignment for 100-pin LGA and 80-/64-pin packages

• Changed the order of Notes in Figures 1.5

15-17

• Added pin No. for 100-pin LGA package to Tables 1.8 to 1.10

19, 20,

22, 23

• Added Tables 1.11 to 1.14 to provide pin characteristics for 80-/64-pin

packages.

• Changed the following expression: “A ceramic resonator or a crystal

oscillator” for “Main clock input/output” in Table 1.15, to “A crystal, or a

ceramic resonator”

• Modified descriptions for

HLDA and RDY of “Bus control pins” in Table

1.16

• Changed the following expression: “selected” for “Input port” in Table

1.17

, to “selectable”

• Modified description “TXD2” for TXD0 to TXD8 of “Serial interface” in

Table 1.17

, to “TXD2 output”

28-30

• Added Tables 1.19 to 1.21 to provide pin definitions and functions for

80-/64-pin packages

Chapter 2. CPU

—

• Made major text modifications to this chapter

• Changed the following expression: “a requested interrupt’s priority

level” in line 2 of 2.1.8.11, to “the interrupt request level”

Chapter 3. Memory

• Made major text modifications to this chapter

• Changed RAM size “40” in line 7 of this chapter, to “63”, and address

“0000A3FFh” in line 8, to “0000FFFFh”

• Added descriptions for 32-Kbyte RAM and 128-Kbyte ROM to Figure

3.1

• Changed two “can be”s in Notes 3 and 4 of Figure 3.1, to “becomes”s

Chapter 4. SFRs

• Changed hexadecimal format of reset values for registers CCR and

FMCR in Table 4.1, to binary

• Added FEBC3 register to addresses 000010h-000011h in Table 4.1

• Changed FEBC register for addresses 00001Ch-00001Dh, to FEBC0

in Table 4.1

• Modified the following register name in Table 4.1: “Chip-select

Boundary (between n and n + 1) Setting Register”, to “Chip-select n

and n + 1 Boundary Setting Register”

REVISION HISTORY

R32C/111 Group Datasheet

Rev.

Date

Description

Page

Summary

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