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ST7263BEx bảng dữ liệu(PDF) 116 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C
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On-chip peripherals
ST7263Bxx
116/186
Doc ID 7516 Rev 8
11.5.5
Low power modes
11.5.6
Interrupts
Figure 49.
Event flags and interrupt generation
1.
EVF can also be set by EV6 or an error from the SR2 register.
The I²C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the
CC register is reset (RIM instruction).
Table 41.
Low power modes
Mode
Description
WAIT
No effect on I²C interface.
I²C interrupts cause the device to exit from Wait mode.
HALT
I²C registers are frozen.
In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The
I²C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Halt mode” capability.
Table 42.
Interrupts
Interrupt event
Event
flag
Enable
control
bit
Exit
from
Wait
Exit
from
Halt
End of Byte Transfer Event
BTF
ITE
Yes
No
Address Matched Event (Slave mode)
ADSL
Yes
No
Start Bit Generation Event (Master mode)
SB
Yes
No
Acknowledge Failure Event
AF
Yes
No
Stop Detection Event (Slave mode)
STOPF
Yes
No
Arbitration Lost Event (Multimaster configuration)
ARLO
Yes
No
Bus Error Event
BERR
Yes
No
BTF
ADSL
SB
AF
STOPF
ARLO
BERR
EVF
INTERRUPT
ITE
(1)



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