ST7263BEx datasheet(103/186 Pages) STMICROELECTRONICS

103 / 186 page

ST7263Bxx

On-chip peripherals

Doc ID 7516 Rev 8

103/186

Control register (CTLR)

Reset value: 0000 0110 (06h)

Device Address register (DADDR)

Reset value: 0000 0000 (00h)

RESUME

PDWN

FSUSP

FRES

Read/write

[7:4] Reserved. Forced by hardware to 0.

3 RESUME Resume.

This bit is set by software to wakeup the Host when the ST7 is in suspend mode.

0: Resume signal not forced

1: Resume signal forced on the USB bus.

Software should clear this bit after the appropriate delay.

2 PDWN Power down.

This bit is set by software to turn off the 3.3 V on-chip voltage regulator that

supplies the external pull-up resistor and the transceiver.

0: Voltage regulator on

1: Voltage regulator off

Note: After turning on the voltage regulator, software should allow at least 3 µs for

stabilization of the power supply before using the USB interface.

1 FSUSP Force suspend mode.

This bit is set by software to enter Suspend mode. The ST7 should also be halted

allowing at least 600 ns before issuing the HALT instruction.

0: Suspend mode inactive

1: Suspend mode active

When the hardware detects USB activity, it resets this bit (it can also be reset by

software).

0 FRES Force reset.

This bit is set by software to force a reset of the USB interface, just as if a RESET

sequence came from the USB.

0: Reset not forced

1: USB interface reset forced.

The USB is held in RESET state until software clears this bit, at which point a “USB-

RESET” interrupt will be generated if enabled.

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

Read.write

7 Reserved. Forced by hardware to 0.

[6:0] ADD[6:0] Device address, 7 bits.

Software must write into this register the address sent by the host during

enumeration.

Note: This register is also reset when a USB reset is received from the USB bus or

forced through bit FRES in the CTLR register.

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