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M32C/86T bảng dữ liệu(PDF) 318 Page - Renesas Technology Corp |
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M32C/86T bảng dữ liệu(HTML) 318 Page - Renesas Technology Corp |
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318 / 505 page  Page 295 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 22. Intelligent I/O (Communication Function) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Figure 22.26 G0IRF Register SI/O Special Communication Interrupt Detect Register 0 (1, 2) Symbol Address After Reset G0IRF 00FE16 0016 RW RW RW RW RW RW RW RW Bit Name Function Bit Symbol Reserved Bit Reserved Bit Set to "0" Set to "0" NOTES: 1. The G0IRF register is used in HDLC data processing mode. Do not use in clock synchronous serial I/O mode. 2. The SRT0R bit in the IIO4IR register is set to "1" if the BSERR or IRF0 to IRF3 bit is set to "1". BSERR (b1 - b0) (b3) Bit Stuffing Error Detect Flag 0 : Not detected 1 : Detected IRF0 IRF1 IRF2 Interrupt Cause Determination Flag 0 IRF3 Interrupt Cause Determination Flag 1 Interrupt Cause Determination Flag 2 Interrupt Cause Determination Flag 3 b7 b6 b5 b4 b3 b2 b1 b0 0 : The G0DR register (receive data register) does not match the G0CMP0 register 1 : The G0DR register matches the G0CMP0 register 0 : The G0DR register (receive data register) does not match the G0CMP1 register 1 : The G0DR register matches the G0CMP1 register 0 : The G0DR register (receive data register) does not match the G0CMP2 register 1 : The G0DR register matches the G0CMP2 register 0 : The G0DR register (receive data register) does not match the G0CMP3 register 1 : The G0DR register matches the G0CMP3 register 00 0 |
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