H8SXSLASH1663R datasheet(299/1504 Pages) RENESAS

tên linh kiện	H8SX/1663R

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 267 of 1468

REJ09B0412-0200

9.8.4

Basic Timing

The number of access cycles in the initial cycle (full access) on the burst ROM interface is

determined by the basic bus interface settings in ABWCR, ASTCR, WTCRA, WTCRB, and bits

CSXHn in CSACR (n = 0 to 7). When area 0 or area 1 designated as burst ROM space is read by

the CPU or EXDMAC cluster transfer, the settings in RDNCR and bits CSXTn in CSACR (n = 0

to 7) are ignored.

From one to eight cycles can be selected for the burst cycle, according to the settings of bits

BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait cycles cannot be inserted. In

addition, 4-word, 8-word, 16-word, or 32-word consecutive burst access can be performed

according to the settings of BSTS01, BSTS00, BSTS11, and BSTS10 bits in BROMCR.

The basic access timing for burst ROM space is shown in figures 9.29 and 9.30.

Upper

address bus

Note: n = 1, 0

Lower

address bus

Data bus

Full access

Burst access

CSn

RD/

Figure 9.29 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)

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