H8SXSLASH1663R datasheet(144/1504 Pages) RENESAS

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Section 5 Voltage Detection Circuit (LVD)

Rev. 2.00 Sep. 24, 2008 Page 112 of 1468

REJ09B0412-0200

5.3.3

Release from Deep Software Standby Mode by the Voltage-Detection Circuit

If the LVDE and LVDRI bits in LVDCR and the DLVDIE bit in DPSIER have all been set to 1

during a period in deep software standby mode, the voltage-detection circuit requests release from

deep software standby mode when Vcc falls to or below Vdet. This sets the DLVDIF bit in

DPSIFR to 1, thus producing release from the deep software standby mode. For the deep software

standby mode, see section 28, Power-Down Modes.

5.3.4

Voltage Monitor

The result of voltage detection by the voltage-detection circuit can be monitored by checking the

value of the LVDMON bit in LVDCR. When the LVDMON bit has been enabled by setting the

LVDE bit, 0 indicates that Vcc is at or below Vdet and 1 indicates that Vcc is above Vdet. This

bit should be read while the voltage-monitoring reset has been disabled by setting the LVDRI bit

to 1.

Before clearing the LVDF bit in RSTSR to 0, confirm that the LVDMON bit is set to 1 (indicating

that Vcc is above Vdet). When it is impossible to clear the LVDF bit despite the LVDMON bit

being 1, the voltage-detection circuit is in the state of waiting for stabilization. In such cases, clear

the bit again after the stabilization time (t

por) has elapsed.

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