H8SXSLASH1663R datasheet(133/1504 Pages) RENESAS

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Section 4 Resets

Rev. 2.00 Sep. 24, 2008 Page 101 of 1468

REJ09B0412-0200

4.4

Pin Reset

This is a reset generated by the

RES pin.

When the

RES pin is driven low, all the processing in progress is aborted and the LSI enters a

reset state. In order to firmly reset the LSI, the

STBY pin should be set to high and the RES pin

should be held low at least for 20 ms at a power-on. During operation, the

RES pin should be held

low at least for 20 states.

4.5

Power-on Reset (POR) (H8SX/1668M Group)

This is an internal reset generated by the power-on reset circuit.

RES is in the high-level state when power is supplied, a power-on reset is generated. After Vcc

has exceeded Vpor and the specified period (power-on reset time) has elapsed, the chip is released

from the power-on reset state. The power-on reset time is a period for stabilization of the external

power supply and the LSI circuit.

RES is at the high-level when the power-supply voltage (Vcc) falls to or below Vpor, a power-

on reset is generated. The chip is released after Vcc has risen above Vpor and the power-on reset

time has elapsed.

After a power-on reset has been generated, the PORF bit in RSTSR is set to 1. The PORF bit is in

a read-only register and is only initialized by a pin reset. Figure 4.2 shows the operation of a

power-on reset.

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