H8SXSLASH1663R datasheet(1317/1504 Pages) RENESAS

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Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1285 of 1468

REJ09B0412-0200

28.12

Usage Notes

28.12.1

I/O Port Status

In software standby mode or deep software standby mode, the I/O port states are retained.

Therefore, there is no reduction in current drawn due to output currents when high-level signals

are being output.

28.12.2

Current Consumption during Oscillation Settling Standby Period

Current consumption increases during the oscillation settling standby period.

28.12.3

Module Stop State of EXDMAC, DMAC, or DTC

Depending on the operating state of the EXDMAC, DMAC, and DTC, bits MSTPA14,

MSTPA13, and MSTPA12 may not be set to 1, respectively. The module stop state setting for the

EXDMAC, DMAC, or DTC should be carried out only when the EXDMAC, DMAC, or DTC is

not activated.

For details, refer to section 10, DMA Controller (DMAC), section 11, EXDMA Controller

(EXDMAC), and section 12, Data Transfer Controller (DTC).

28.12.4

On-Chip Peripheral Module Interrupts

Relevant interrupt operations cannot be performed in a module stop state. Consequently, if the

module stop state is entered when an interrupt has been requested, it will not be possible to clear

the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be

disabled before entering a module stop state.

28.12.5

Writing to MSTPCRA, MSTPCRB, and MSTPCRC

MSTPCRA, MSTPCRB, and MSTPCRC should only be written to by the CPU.

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