H8SXSLASH1663R datasheet(887/1504 Pages) RENESAS

tên linh kiện	H8SX/1663R

Giải thích chi tiết về linh kiện	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 18 Watchdog Timer (WDT)

Rev. 2.00 Sep. 24, 2008 Page 855 of 1468

REJ09B0412-0200

Section 18 Watchdog Timer (WDT)

The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (

WDTOVF) if a

system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At

the same time, the WDT can also generate an internal reset signal.

When this watchdog function is not needed, the WDT can be used as an interval timer. In interval

timer operation, an interval timer interrupt is generated each time the counter overflows.

Figure 18.1 shows a block diagram of the WDT.

18.1

Features

• Selectable from eight counter input clocks

• Switchable between watchdog timer mode and interval timer mode

 In watchdog timer mode

If the counter overflows, the WDT outputs

WDTOVF. It is possible to select whether or

not the entire LSI is reset at the same time.

 In interval timer mode

If the counter overflows, the WDT generates an interval timer interrupt (WOVI).

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