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H8SX/1663R bảng dữ liệu(HTML) 333 Page - Renesas Technology Corp |
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333 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 301 of 1468 REJ09B0412-0200 (2) Self-Refresh Mode Some DRAMs have a self-refresh mode (battery backup mode). The self-refresh mode is a kind of standby mode and refresh timing and refresh address are controlled internally. The self-refresh mode is selected by setting the RFSHE and SLFRF bits in REFCR to 1. The CAS and RAS signals are output as shown in figure 9.56 by executing the SLEEP instruction. Then, DRAM enters self-refresh mode. When a CBR refresh is requested on a transition to the standby mode, the CBR refresh is first performed and then the self-refresh mode is entered. When the self-refresh mode is used, do not clear the OPE bit in SBYCR to 0. For details, see section 28.2.1, Standby Control Register (SBYCR). TRp TRr TRc3 B φ RAS LUCAS LLCAS WE BS RD/ WR High Software standby TRc4 High High Figure 9.56 Self-Refresh Timing |
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