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M32C/8A bảng dữ liệu(PDF) 247 Page - Renesas Technology Corp |
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M32C/8A bảng dữ liệu(HTML) 247 Page - Renesas Technology Corp |
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247 / 372 page  M32C/8A Group 17. Serial Interfaces Rev.1.00 Jul 15, 2007 Page 230 of 352 REJ09B0385-0100 Figure 17.24 Transfer Timing to the UiRB Register and Interrupt Timing SCLi (1) When the IICM2 bit is set to 0 (ACK or NACK interrupt) and the CKPH bit is set to 0 (no clock delay) D7 D6 D4 D3 D2 D1 D5 SDAi i = 0 to 4 The above applies when the CKDIR bit in UiMR register = 1 (external clock selected) D0 D8 (ACK,NACK) ACK interrupt (DMA request) or NACK interrupt Transferred to the UiRB register D8 D7 D6 D5 D4 D3 D2 D1 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15 b9 b8 b7 b0 SCLi (2) When the IICM2 bit is set to 0 and the CKPH bit is set to 1 (clock delay) D7 D6 D4 D3 D2 D1 D5 SDAi D0 D8 (ACK, NACK) SCLi (3)When the IICM2 bit is set to 1 (UART transmit or receive interrupt) and the CKPH bit is set to 0 D7 D6 D4 D3 D2 D1 D5 SDAi D0 D8 (ACK,NACK) ACK interrupt (DMA request) or NACK interrupt Transferred to the UiRB register D8 D7 D6 D5 D4 D3 D2 D1 b15 b9 b8 b7 b0 Receive interrupt (DMA request) Transmit interrupt D0 − D7 D6 D5 D4 D3 D2 b15 b9 b8 b7 b0 SCLi (4) When the IICM2 bit is set to 1 and the CKPH bit is set to 1 D7 D6 D4 D3 D2 D1 D5 SDAi D0 D8 (ACK, NACK) Contents of the UiRB register Contents of the UiRB register Transferred to the UiRB register Contents of the UiRB register Receive interrupt (DMA request) Transmit interrupt D0 − D7 D6 D5 D4 D3 D2 b15 b9 b8 b7 b0 Transferred to the UiRB register (first time) Contents of the UiRB register Transferred to the UiRB register (second time) D8 D7 D6 D5 D4 D3 D2 D1 b15 b9 b8 b7 b0 Contents of the UiRB register D0 D0 D1 D0 D1 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit |
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