M32CSLASH8A datasheet(236/372 Pages) RENESAS

236 / 372 page

M32C/8A Group

17. Serial Interfaces

Rev.1.00

Jul 15, 2007

Page 219 of 352

REJ09B0385-0100

Figure 17.18

Transmit Operation in UART Mode

Stop bit

Parity bit

Start bit

(1) Example of the transmit operation timing in 8-bit data length (parity enabled, 1 stop bit)

Transmission stops because TE = 0

TE bit in the

UiC1 register

The above applies under the following conditions:

- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)

- UiC0 register: CRD bit = 0 and CRS bit = 0 (CTS function used)

- UiC1 register: UiIRS bit = 1 (transmit interrupt is generated when the transmit operation is completed)

Internal transmit

clock

TI bit in the UiC1

Write data to UiTB register

CTSi input

“H”

“L”

Transfer data from UiTB register to UARTi transmit shift register

TXDi output

TXEPT bit in the

UiC0 register

IR bit in the

SiTIC register

Set to 0 by an interrupt request acknowledgement or by program

D1 D2 D3 D4 D5 D6

D0 D1 D2 D3 D4 D5 D6

Stop bits

Start bit

(2) Example of the transmit operation timing in 9-bit data length (parity disabled, 2 stop bit)

TE bit in the

UiC1 register

The above applies under the following conditions:

- UiMR register: PRYE bit = 0 (parity disabled), STPS bit = 1 (2 stop bits)

- UiC0 register: CRD bit = 1 (CTS function disabled)

- UiC1 register: UiIRS bit = 0 (transmit interrupt is generated when no data in the UiTB register)

TI bit in the UiC1

Write data to UiTB register

Transfer data from UiTB register to UARTi transmit shift register

TXDi output

TXEPT bit in the

UiC0 register

IR bit in the

SiTIC register

Set to 0 by an interrupt request acknowledgement or by program

16(m + 1)

TC =

i = 0 to 4

NOTE:

1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).

D1 D2 D3 D4 D5 D6

D0 D1 D2 D3 D4 D5 D6

Internal transmit

clock

“H”

“L”

“H”

“L”

fj: f1, f8, f2n(1), fEXT

fEXT: clock input to the CLKi pin when the external clock is selected

m: setting value of the UiBRG register (00h to FFh)

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