M32CSLASH8A datasheet(231/372 Pages) RENESAS

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M32C/8A Group

17. Serial Interfaces

Rev.1.00

Jul 15, 2007

Page 214 of 352

REJ09B0385-0100

17.1.1.3 Serial Data Logic Inverse

When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted

for transmit operation. A read from the UiRB register returns the inverted logic of receive data. Figure 17.16

shows an example of serial data logic inverse operation.

Figure 17.16

Serial Data Logic Inverse

Serial clock

(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)

(2) When the UiLCH bit is set to 1 (inverted)

TXDi

(not inverted)

The above applies under the following conditions:

- CKPOL bit in the UiC0 register is set to 0 (transmit data is output at the falling edge and received data is input at the rising edge)

- UFORM bit in the UiC0 register is set to 0 (LSB first).

"H"

"L"

"H"

"L"

Serial clock

TXDi

(inverted)

"H"

"L"

"H"

"L"

RXDi

(not inverted)

"H"

"L"

RXDi

(inverted)

"H"

"L"

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