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M306V2EEFS bảng dữ liệu(PDF) 168 Page - Renesas Technology Corp |
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M306V2EEFS bảng dữ liệu(HTML) 168 Page - Renesas Technology Corp |
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168 / 271 page ![]() Rev.1.40 Oct 06, 2004 page 168 of 269 M306V2ME-XXXFP, M306V2EEFP Figures 2.14.4 and 2.14.5 the data slicer control registers. Figure 2.14.4 Data slicer control register 1 Figure 2.14.5 Data slicer control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Data slicer control register 1 00 Reserved bits 00 0 Definition of fields 1 (F1) and 2 (F2) Hsep Vsep F1: Hsep Vsep F2: R W Bit name Function Must always be set to “0” Symbol Address When reset DSC1 026016 0016 Bit symbol DSC10 DSC11 DSC12 Reference clock source selection bit Data slicer and timing signal generating circuit control bit 0: F2 1: F1 Selection bit of data slice reference voltage generating field 0: Stopped 1: Operating 0: Video signal 1: HSYNC signal b7 b6 b5 b4 b3 b2 b1 b0 R W Data slicer control register 2 00 0: Data is not latched yet and a clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. Caption data latch completion flag 1 Reserved bit Read-only Test bit 0: F2 1: F1 Field determination flag 0: Method (1) 1: Method (2) Vertical synchronous signal (Vsep) generating method selection bit 0: Match 1: Mismatch V-pulse shape determination flag Function Bit name Definition of fields 1 (F1) and 2 (F2) Hsep Vsep F1: Hsep Vsep F2: Bit symbol DSC20 DSC23 DSC24 DSC25 Symbol Address When reset DSC2 026116 ?0?0??0?2 Must always be set to “0” Reserved bit Must always be set to “0” Read-only Test bit |
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