M306V2EEFS datasheet(149/271 Pages) RENESAS

149 / 271 page

Rev.1.40

Oct 06, 2004 page 149 of 269

M306V2ME-XXXFP, M306V2EEFP

Table 2.12.1 Performance of A-D converter

Item

Performance

Method of A-D conversion Successive approximation (capacitive coupling amplifier)

Analog input voltage (Note 1) 0V to AVCC (VCC)

Operating clock

φAD (Note 2) fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)

Resolution8-bit

Absolute precisionVCC = 5V

• Without sample and hold function: ±5 LSB

• With sample and hold function: ±5 LSB

Operating modes

One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

and repeat sweep mode 1

Analog input pins

6 pins (AN0 to AN5)

A-D conversion start condition • Software trigger

A-D conversion starts when the A-D conversion start flag changes to “1”

Conversion speed per pin • Without sample and hold function

φAD cycles

• With sample and hold function

φAD cycles

2.12 A-D Converter

The A-D converter consists of one 8-bit successive approximation A-D converter circuit with a capacitive coupling

amplifier. Pins P102 to P107 also function as the analog signal input pins. The direction registers of these pins for A-

D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the

resistance ladder of the A-D converter from the reference voltage (VREF) when the A-D converter is not used. Doing

so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-

D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF.

The result of A-D conversion is stored in the A-D registers of the selected pins.

Table 2.12.1 shows the performance of the A-D converter. Figure 2.12.1 shows the block diagram of the A-

D converter, and Figures 2.12.2 to 2.12.5 show the A-D converter-related registers.

Notes 1: Does not depend on use of sample and hold function.

2: Divide the frequency if f(XIN) exceeds 10 MHz, and make

φAD frequency equal to 10 MHz. Without

sample and hold function, set the

φAD frequency to 250kHz min.

With the sample and hold function, set the

φAD frequency to 1MHz min.

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