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M306V2EEFS bảng dữ liệu(PDF) 129 Page - Renesas Technology Corp |
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M306V2EEFS bảng dữ liệu(HTML) 129 Page - Renesas Technology Corp |
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129 / 271 page  Rev.1.40 Oct 06, 2004 page 129 of 269 M306V2ME-XXXFP, M306V2EEFP Table 2.11.13 Multi-master I2C-BUS Interface Functions Item Function Format In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode Communication mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception SCL clock frequencyn 16.1 kHz to 400 kHz (at BCLK = 10 MHz) Note : We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 027D16) for connections between the I2C-BUS interface 0 and ports (SCL1, SCL2, SDA1, SDA2). 2.11.6 Multi-master I2C-BUS Interface 0 and Multi-master I2C-BUS Interface 1 The multi-master I2C-BUS interface 0 and 1 have each dedicated circuit and operate independently. The multi-master I2C-BUS interface i is a serial communications circuit, conforming to the Philips I2C- BUS data transfer format. This interface i, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figures 2.11.32 and 2.11.33 show a block diagram of the multi-master I2C-BUS interface i and Table 2.11.13 shows multi-master I2C-BUS interface i functions. This multi-master I2C-BUS interface i consists of the I2Ci address register, the I2Ci data shift register, the I2Ci clock control register, the I2Ci control register, the I2Ci status register, the I2Ci port selection register and other control circuits. |
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