AT80SND1C-ROTIL datasheet(160/210 Pages) ATMEL

160 / 210 page

160

AT8xC51SND1C

4109E–8051–06/03

Bit Rate

The bit rate can be selected from seven predefined bit rates or from a programmable bit

rate generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see

Table 142). The predefined bit rates are derived from the peripheral clock (F

PER) issued

from the Clock Controller block as detailed in section "Oscillator", page 12, while bit rate

generator is based on timer 1 overflow output.

Note:

1. These bit rates are outside of the low speed standard specification limited to 100 kHz

but can be used with high speed TWI components limited to 400 kHz.

Master Transmitter Mode

In the master transmitter mode, a number of data Bytes are transmitted to a slave

receiver (see Figure 125). Before the master transmitter mode can be entered, SSCON

must be initialized as follows:

SSCR2:0 define the serial bit rate (see Table 135). SSPE must be set to enable the con-

troller. SSSTA, SSSTO and SSI must be cleared.

The master transmitter mode may now be entered by setting the SSSTA bit. The TWI

logic will now monitor the TWI bus and generate a START condition as soon as the bus

becomes free. When a START condition is transmitted, the serial interrupt flag (SSI bit

in SSCON) is set, and the status code in SSSTA is 08h. This status must be used to

vector to an interrupt routine that loads SSDAT with the slave address and the data

direction bit (SLA+W). The serial interrupt flag (SSI) must then be cleared before the

serial transfer can continue.

When the slave address and the direction bit have been transmitted and an acknowl-

edgment bit has been received, SSI is set again and a number of status code in SSSTA

are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if

the slave mode was enabled (SSAA = logic 1). The appropriate action to be taken for

each of these status code is detailed in Table 136. This scheme is repeated until a

STOP condition is transmitted.

SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in

Table 136. After a repeated START condition (state 10h) the controller may switch to

the master receiver mode by loading SSDAT with SLA+R.

Table 135. Serial Clock Rates

SSCRx

Bit Frequency (kHz)

PER Divided By

210

PER = 6 MHz

PER = 8 MHz

PER = 10 MHz

62.5

78.125

256

53.5

71.5

89.3

224

62.5

104.2(1)

192

100

125(1)

160

12.5

16.5

20.83

960

100

133.3(1)

166.7(1)

120

110

200(1)

266.7(1)

333.3(1)

0.5 <

⋅ < 125(1)

0.67 <

⋅ < 166.7(1) 0.81 < ⋅ < 208.3(1) 96 ⋅ (256 – reload value Timer 1)

SSCR2

SSPE

SSSTA

SSSTO

SSI

SSAA

SSCR1

SSCR0

Bit Rate

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