AT80SND1C-ROTIL datasheet(138/210 Pages) ATMEL

138 / 210 page

138

AT8xC51SND1C

4109E–8051–06/03

Framing Error Detection

(Modes 1, 2 and 3)

Framing error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register as shown in

Figure 104.

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by 2 devices. If a valid stop bit is not found, the software sets FE bit in

SCON register.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a chip reset clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on

stop bit instead of the last data bit as detailed in Figure 110.

Figure 104. Framing Error Block Diagram

Baud Rate Selection (Modes 1

and 3)

In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud

Rate Generator and allows different baud rate in reception and transmission.

As shown in Figure 105 the selection is done using RBCK and TBCK bits in BDRCON

Figure 106 gives the baud rate calculation formulas for each baud rate source while

Table 124 details Internal Baud Rate Generator configuration for different peripheral

clock frequencies and giving baud rates closer to the standard baud rates.

Figure 105. Baud Rate Source Selection (Modes 1 and 3)

Figure 106. Baud Rate Formulas (Modes 1 and 3)

SM0

SMOD0

PCON.6

SM0/FE

SCON.7

Framing Error

Controller

RBCK

BDRCON.2

CLOCK

To Serial

IBRG

CLOCK

Rx Port

TBCK

BDRCON.3

CLOCK

To Serial

IBRG

CLOCK

Tx Port

÷ 16

Baud_Rate=

(1-SPD)

⋅ 32 ⋅ (256 -BRL)

2SMOD1

⋅ F

PER

BRL= 256 -

6(1-SPD)

⋅ 32 ⋅ Baud_Rate

SMOD1

⋅ FPER

Baud_Rate=

6 Þ 32 Þ (256 -TH1)

2SMOD1

⋅ FPER

TH1= 256 -

192

⋅ Baud_Rate

SMOD1

⋅ FPER

a. IBRG Formula

b. T1 Formula

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