AT80SND1C-ROTIL datasheet(126/210 Pages) ATMEL

126 / 210 page

126

AT8xC51SND1C

4109E–8051–06/03

Table 113. MMCON1 Register

MMCON1 (S:E5h) – MMC Control Register 1

Reset Value = 0000 0000b

Table 114. MMCON2 Register

MMCON2 (S:E6h) – MMC Control Register 2

Reset Value = 0000 0000b

7654

3210

BLEN3

BLEN2

BLEN1

BLEN0

DATDIR

DATEN

RESPEN

CMDEN

Bit

Number

Bit

Mnemonic

Description

7 - 4

BLEN3:0

Block Length Bits

Refer to Table 111 for bits description. Do not program value > 1011b

3DATDIR

Data Direction Bit

Set to select data transfer from host to card (write mode).

Clear to select data transfer from card to host (read mode).

2DATEN

Data Transmission Enable Bit

Set and clear to enable data transmission immediately or after response has

been received.

RESPEN

Response Enable Bit

Set and clear to enable the reception of a response following a command

transmission.

0CMDEN

Command Transmission Enable Bit

Set and clear to enable transmission of the command FIFO to the card.

7654

3210

MMCEN

DCR

CCR

DATD1

DATD0

FLOWC

Bit

Number

Bit

Mnemonic

Description

7MMCEN

MMC Clock Enable Bit

Set to enable the MCLK clocks and activate the MMC controller.

Clear to disable the MMC clocks and freeze the MMC controller.

DCR

Data Controller Reset Bit

Set and clear to reset the data line controller in case of transfer abort.

CCR

Command Controller Reset Bit

Set and clear to reset the command line controller in case of transfer abort.

4-3

Reserved

The value read from these bits is always 0. Do not set these bits.

2-1

DATD1:0

Data Transmission Delay Bits

Used to delay the data transmission after a response from 3 MMC clock periods

(all bits cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock

periods.

0FLOWC

MMC Flow Control Bit

Set to enable the flow control during data transfers.

Clear to disable the flow control during data transfers.

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