ADE7566 datasheet(117/136 Pages) AD

117 / 136 page

Preliminary Technical Data

ADE7566/ADE7569

Rev. PrA | Page 117 of 136

Timer 2 is selected as the baud rate generator by setting TCLK

and/or RCLK in Timer/Counter 2 Control SFR (T2CON, 0xC8).

The baud rates for transmit and receive can be simultaneously

different. Setting RCLK and/or TCLK puts Timer 2 into its baud

rate generator mode as shown in Figure 92.

In this case, the baud rate is given by the following formula:

Mode 1 and Mode 3 Baud Rate =

()

[]

()

RCAP

CORE

65536

−

UART Timer Generated Baud Rates

The high integer dividers in a UART block mean that high speed

baud rates are not always possible. In addition, generating baud

rates requires the exclusive use of a timer, rendering it unusable

for other applications when the UART is required. To address

this problem, each ADE7566/ADE7569 has a dedicated baud

rate timer (UART timer) specifically for generating highly

accurate baud rates. The UART timer can be used instead of

Timer 1 or Timer 2 for generating very accurate high speed

UART baud rates, including 115,200 bps. This timer also allows

a much wider range of baud rates to be obtained. In fact, every

desired bit rate from 12 bps to 393,216 bps can be generated to

within an error of ±0.8%. The UART timer also frees up the other

three timers, allowing them to be used for different applications.

A block diagram of the UART timer is shown in Figure 91.

÷(1 + SBAUDF/64)

UART TIMER

Rx/Tx CLOCK

fCORE

UARTBAUDEN

Rx CLOCK

Tx CLOCK

TIMER 1/TIMER 2

Rx CLOCK

FRACTIONAL

DIVIDER

TIMER 1/TIMER 2

Tx CLOCK

÷32

÷2DIV + SBTH

Figure 91. UART Timer, UART Baud Rate

Two SFRs, Enhanced Serial Baud Rate Control SFR (SBAUDT,

0x9E) and UART Timer Fractional Divider SFR (SBAUDF,

0x9D), are used to control the UART timer. SBAUDT is the

baud rate control SFR; it sets up the integer divider (DIV) and

the extended divider (SBTH) for the UART timer.

The appropriate value to write to the DIV[2:0] and SBTH[1:0]

bits can be calculated using the following formula where fCORE is

defined in the POWCON SFR (see

Table 23). Note that the DIV value must be rounded down to

the nearest integer.

()

log

⎟

⎠

⎞

⎜

⎝

⎛

Rate

Baud

SBTH

DIV

CORE

fCORE

TR2

CONTROL

TL2

(8 BITS)

TH2

(8 BITS)

RELOAD

EXEN2

CONTROL

T2EX

TRANSITION

DETECTOR

EXF 2

TIMER 2

INTERRUPT

RCAP2L

RCAP2H

TIMER 2

OVERFLOW

RCLK

TCLK

CLOCK

SMOD

TIMER 1

OVERFLOW

C/ T2 = 0

C/ T2 = 1

NOTE: AVAILABILITY OF ADDITIONAL

EXTERNAL INTERRUPT

Figure 92. Timer 2, UART Baud Rates

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