ST92F120JR9T datasheet(279/320 Pages) STMICROELECTRONICS

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J1850 Byte Level Protocol Decoder (JBLPD)

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

JBLPD CURRENT REGISTER 0 (CREG0)

R252- Read/Write

Reset Value: xxxx xxxx (xxh)

Depending on the RSEL[3:0] value of the OP-

TIONS register, this register is one of the following

stacked registers: RDAPR, FREG0, FREG4,

FREG8, FREG12, FREG16, FREG20, FREG24,

FREG28.

JBLPD CURRENT REGISTER 1 (CREG1)

R253 - Read/Write

Reset Value: xxxx xxxx (xxh)

Depending on the RSEL[3:0] value of the OP-

TIONS register, this register is one of the following

stacked registers: RDCPR, FREG1, FREG5,

FREG9, FREG13, FREG17, FREG21, FREG25,

FREG29.

JBLPD CURRENT REGISTER 2 (CREG2)

R254- Read/Write

Reset Value: xxxx xxxx (xxh)

Depending on the RSEL[3:0] value of the OP-

TIONS register, this register is one of the following

stacked registers:

TDAPR, FREG2, FREG6,

FREG10, FREG14, FREG18, FREG22, FREG26,

FREG30.

JBLPD CURRENT REGISTER 3 (CREG3)

R255- Read/Write

Reset Value: xxxx xxxx (xxh)

Depending on the RSEL[3:0] value of the OP-

TIONS register, this register is one of the following

stacked registers: TDCPR, FREG3, FREG7,

FREG11, FREG15, FREG19, FREG23, FREG27,

FREG31.

Table 54. Stacked registers map

RSEL[3:0]

Current

Registers

0000b

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

CREG0

RDAPR

FREG0

FREG4

FREG8

FREG12

FREG16

FREG20

FREG24

FREG28

CREG1

RDCPR

FREG1

FREG5

FREG9

FREG13

FREG17

FREG21

FREG25

FREG29

CREG2

TDAPR

FREG2

FREG6

FREG10

FREG14

FREG18

FREG22

FREG26

FREG30

CREG3

TDCPR

FREG3

FREG7

FREG11

FREG15

FREG19

FREG23

FREG27

FREG31

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